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CAT24FC256
256K-Bit I2C Serial CMOS EEPROM FEATURES
I Fast mode I2C bus compatible* I Max clock frequency: I Industrial and automotive
temperature ranges
I 5 ms max write cycle time I Write protect feature I 100,000 program/erase cycles I 100 year data retention
- 400kHz for VCC = 1.8 V to 5.5 V - 1MHz for VCC = 2.5 V to 5.5 V
I Schmitt trigger filtered inputs for noise suppression I Low power CMOS technology I 64-byte page write buffer I Self-timed write cycle with auto-clear
- Entire array protected when WP at VIH
I 8-pin DIP or 8-pin SOIC(JEDEC) and 8-pin SOIC
(EIAJ)
DESCRIPTION
The CAT24FC256 is a 256K-bit Serial CMOS EEPROM internally organized as 32,768 words of 8 bits each. Catalyst's advanced CMOS technology substantially reduces device power requirements. The CAT24FC256
features a 64-byte page write buffer. The device operates via the I2C bus serial interface and is available in 8pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P, L, GL)
A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA
SOIC Package (J, W, K, X, GW, GX)
PIN FUNCTIONS
Pin Name A0, A1, A2 SDA SCL WP VCC VSS NC
is D
A0 A1 A2 VSS 2 3 4
1
o c
8 7 6 5 VCC WP SCL SDA
i t n
u n
EXTERNAL LOAD VCC VSS SDA
BLOCK DIAGRAM
d e
DOUT ACK CONTROL LOGIC
a P
t r
SENSE AMPS SHIFT REGISTERS
WORD ADDRESS BUFFERS
COLUMN DECODERS 512
START/STOP LOGIC
XDEC WP
512
EEPROM 512X512
Function
DATA IN STORAGE
Address Inputs Serial Data/Address
Serial Clock Write Protect +1.8V to +5.5V Power Supply Ground
A0 A1 A2 SLAVE ADDRESS COMPARATORS SCL STATE COUNTERS
HIGH VOLTAGE/ TIMING CONTROL
No Connect
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1040, Rev. K
CAT24FC256
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. -55C to +125C Storage Temperature ....................... -65C to +150C Voltage on Any Pin with Respect to Ground(1) ........... -2.0V to +VCC + 2.0V VCC with Respect to Ground ............... -2.0V to +7.0V Package Power Dissipation Capability (TA = 25C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol NEND TDR
(3) (3)
*COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
Parameter Endurance Data Retention Latch-up
Reference Test Method MIL-STD-883, Test Method 1008 JEDEC Standard 17
Min 100
Typ
MIL-STD-883, Test Method 1033 100,000
ILTH(3)(4)
DC OPERATING CHARACTERISTICS VCC = 1.8 V to 5.5 V, unless otherwise specified. Symbol ICC1 ICC2 ISB(5) ILI ILO VIL VIH VOL1 VOL2 Parameter Power Supply Current - Read Power Supply Current - Write Standby Current
Input Leakage Current
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol Test CI/O(3) CIN
(3)
is D
Output Leakage Current Input Low Voltage
Input High Voltage
Output Low Voltage (VCC = +3.0 V) Output Low Voltage (VCC = +1.8 V)
o c
i t n
Test Conditions fSCL = 100kHz VCC = 5V
fSCL = 400kHz VCC = 5V
VIN = GND or VCC VCC = 5V VIN = GND to VCC
u n
Min
d e
100
a P
Max Max 400 4 1 1 1 VCC x 0.3 VCC + 0.5 0.4 0.5
Units
Cycles/Byte Years mA
t r
A mA A A A V V V V
Typ
Units
VOUT = GND to VCC -0.5 VCC x 0.7 IOL = 3.0 mA IOL = 1.5 mA
Conditions VI/O = 0V VIN = 0V
Min
Typ
Max 8 6
Units pF pF
Input/Output Capacitance (SDA) Input Capacitance (SCL, WP, A0, A1)
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and JEDEC test methods. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V. (5) Maximum standby current (ISB ) = 10A for the Automotive and Extended Automotive temperature range.
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC256
AC CHARACTERISTICS VCC = 1.8V to 5.5 V, unless otherwise specified. Output load is 1 TTL gate and 100pF. Read & Write Cycle Limits Symbol Parameter VCC=1.8V - 5.5V Min FSCL tAA tBUF(2) tHD:STA tLOW tHIGH tSU:STA tHD:DAT tSU:DAT tR(2) tF(2) tSU:STO tDH tWR tSP tSU;WP tHD;WP Clock Frequency SCL Low to SDA Data Out and ACK Out Time the Bus Must be Free Before a New Transmission Can Start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time 0.05 1.3 0.6 1.3 0.6 0.6 Max 400 0.9 0.05 0.5 0.25 0.6 VCC=2.5V - 5.5V Min Max 1000 0.5 Units
Stop Condition Setup Time Data Out Hold Time Write Cycle Time
Input Suppresssion (SDA, SCL) WP Setup Time WP Hold Time
Power-Up Timing (2)(3)
Symbol tPUR
tPUW
Note: (1) AC measurement conditions: RL (connects to VCC): 0.3VCC to 0.7 VCC Input rise and fall times: < 50ns Input and output timing reference voltages: 0.5 VCC (2) This parameter is tested initially and after a design or process change that affects the parameter. (3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
D
is
o c
i t n
u n
100 20 20 0.6 50 0.6 1.3
0
0.3
300
d e
0 50 5
Typ
0.4
0.25
a P
0.1 100 5 50
t r
s s s s s s ns ns s ns s ns ms ns s s
kHz
100
0.25
50 0.5 0.8
Parameter
Min
Max 1 1
Units ms ms
Power-Up to Read Operation Power-Up to Write Operation
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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CAT24FC256
FUNCTIONAL DESCRIPTION
The CAT24FC256 supports the I2C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC256 operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs.
WP: Write Protect
This input, when tied to GND, allows write operations to the entire memory. When this pin is tied to Vcc, the entire memory is write protected. When left floating, memory is unprotected.
PIN DESCRIPTIONS SCL: Serial Clock
The serial clock input clocks all data transferred into or out of the device.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left connected. When hardwired, up to eight CAT24FC256's may be addressed on a single bus system. When the pins are left unconnected, the default values are zero.
Figure 1. Bus Timing
tF tLOW SCL tSU:STA tHD:STA tHIGH tLOW tR
SDA IN
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
Figure 3. Start/Stop Timing
D
is
SDA SCL
8TH BIT BYTE n
o c
START BIT
i t n
tHD:DAT tAA
u n
tDH
tWR
tSU:DAT
d e
a P
tSU:STO tBUF
t r
ACK
STOP CONDITION
START CONDITION
ADDRESS
STOP BIT
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC256
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT24FC256 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. as many as eight devices on the same bus. These bits must compare to their hardwired input pins. The last bit of the slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master sends a START condition and the slave address byte, the CAT24FC256 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC256 then performs a Read or Write operation depending on the state of the R/W bit. Acknowledge
After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a START condition. The Master sends the address of the particular slave device it is requesting. The four most significant bits of the 8-bit slave address are fixed as 1010 (Fig. 5). The CAT24FC256 uses the next three bits as address bits. The address bits A2, A1 and A0 allow
Figure 4. Acknowledge Timing
is D
SCL FROM MASTER
DATA OUTPUT FROM TRANSMITTER
o c
1
i t n
1
u n
The CAT24FC256 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. When the CAT24FC256 begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC256 will continue to transmit
d e
8
a P
t r
9
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 5. Slave Address Bits
0 1 0 A2 A1 A0 R/W
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1040, Rev. K
CAT24FC256
data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. If the Master transmits more than 64 bytes before sending the STOP condition, the address counter `wraps around', and previously transmitted data will be overwritten. When all 64 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24FC256 in a single write cycle. Acknowledge Polling
WRITE OPERATIONS
Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24FC256. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24FC256 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Page Write The CAT24FC256 writes up to 64 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 63 additional bytes. After each byte has been transmitted, CAT24FC256 will respond with an acknowledge, and internally increment the six low order address bits by one. The high order bits remain unchanged. Figure 6. Byte Write Timing
Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, CAT24FC256 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24FC256 is still busy with the write operation, no ACK will be returned. If CAT24FC256 has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation.
BUS ACTIVITY: MASTER
*=Don't Care Bit
Figure 7. Page Write Timing
S T A R T
D
S
SDA LINE
is
S
SLAVE ADDRESS
S T A R T
o c
SLAVE ADDRESS
i t n
*
u n
A C K
WRITE PROTECTION
The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is tied to VCC, the entire memory array is protected and becomes read only. The CAT24FC256 will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device's failure to send an acknowledge after the first byte of data is received.
d e
DATA A C K
a P
S T O P P A C K
t r
BYTE ADDRESS A15-A8 A7-A0
A C K
BUS ACTIVITY: MASTER SDA LINE
BYTE ADDRESS A15-A8 A7-A0
DATA
DATA n
DATA n+63
S T O P P
*
A C K A C K A C K A C K A C K A C K A C K
*=Don't Care Bit
Doc. No. 1040, Rev. K
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC256
READ OPERATIONS
The READ operation for the CAT24FC256 is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT24FC256's address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was to address N, the READ immediately following would access data from address N+1. If N=E (where E=32767), then the counter will `wrap around' to address 0 and continue to clock out data. After the CAT24FC256 receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a `dummy' write operation by sending the START condition,
slave address and byte addresses of the location it wishes to read. After CAT24FC256 acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24FC256 then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. Sequential Read
The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC256 sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC256 will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. The data being transmitted from CAT24FC256 is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24FC256 address bits so that the entire memory array can be read during one operation. If more than E (where E=32767) bytes are read out, the counter will `wrap around' and continue to clock out data bytes.
Figure 8. Immediate Address Read Timing
is D
SCL SDA
o c
BUS ACTIVITY: MASTER SDA LINE
i t n
S T A R T SLAVE ADDRESS S 8
u n
DATA A C K 9
d e
S T O P P N O A C K
a P
t r
8TH BIT DATA OUT NO ACK STOP
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1040, Rev. K
CAT24FC256
Figure 9. Selective Read Timing
BUS ACTIVITY: MASTER SDA LINE
S T A R T S
SLAVE ADDRESS
BYTE ADDRESS A15-A8 A7-A0
S T A R T S
SLAVE ADDRESS
DATA
S T O P P
*
A C K A C K A C K
A C K
*=Don't Care Bit
Figure 10. Sequential Read Timing
BUS ACTIVITY: MASTER SDA LINE A C K A C K SLAVE ADDRESS
DATA n
DATA n+1
DATA n+2
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Doc. No. 1040, Rev. K
o c
i t n
u n
A C K
d e
A C K
a P
DATA n+x S T O P P N O A C K
N O A C K
t r
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC256
PACKAGE OUTLINES 8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17) 0.295 (7.49)
0.355 (9.02) 0.400 (10.16) 0.120 (3.05) 0.150 (3.81) 0.180 (4.57) MAX
0.300 (7.62) 0.325 (8.26)
0.015 (0.38) -- 0.100 (2.54) BSC 0.045 (1.14) 0.060 (1.52) 0.014 (0.36) 0.022 (0.56)
0.110 (2.79) 0.150 (3.81)
Notes: 1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters.
is D
o c
i t n
u n
d e
a P
t r
0.310 (7.87) 0.380 (9.65)
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1040, Rev. K
CAT24FC256
8-LEAD 150 MIL WIDE SOIC (J, W, GW)
0.1890 (4.80) 0.1968 (5.00) 0.149 (3.80) 0.1574 (4.00) 0.2284 (5.80) 0.2440 (6.20) 0.050 (1.27) BSC 0.013 (0.33) 0.020 (0.51) 0.0532 (1.35) 0.0688 (1.75)
0.0040 (0.10) 0.0098 (0.25)
0.0099 (0.25) X 45 0.0196 (0.50) 0.0075 (0.19) 0.0098 (0.25) 0-8
0.016 (0.40) 0.050 (1.27)
Notes: 1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent. 2. All linear dimensions are in inches and parenthetically in millimeters. 3. Lead coplanarity is 0.004" (0.102mm) maximum.
8-LEAD 250 MIL WIDE SOIC (K, X, GX)
0.0267 (0.68) 0.0303 (0.77)
4 REF
is D
o c
0.205 (5.20) 0.213 (5.40)
i t n
u n
d e
a P
0.080 (2.03) MAX
t r
0.205 (5.15) 0.210 (5.35)
0.303 (7.70) 0.318 (8.10) 0.046 (1.17) 0.054 (1.37) 0.0137 (0.35) 0.0177 (0.45)
0.008 (0.20)
0.025 (0.65) Notes: 1. All linear dimensions are in inches and parenthetically in millimeters. 2. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 1040, Rev. K
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT24FC256
ORDERING INFORMATION
Prefix CAT
Device # 24FC256 J
Suffix I -1.8 TE13 REV-A
Optional Company ID
Product Number
Temperature Range I = Industrial (-40C to 85C) A = Automotive (-40C to 105C) E = Extended (-40C to 125C)
Tape & Reel
Package P: PDIP K: SOIC, EIAJ J: SOIC, JEDEC L: PDIP (Lead-free, Halogen-free) W: SOIC, JEDEC (Lead-free, Halogen-free) X: SOIC, EIAJ (Lead-free, Halogen-free) GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating) GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating) GX: SOIC, EIAJ (Lead-free, Halogen-free, NiPdAu lead plating)
Notes: (1) The device used in the above example is a 24FC256JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, Tape & Reel)
is D
o c
i t n
u n
d e
Operating Voltage Blank: 2.5 to 5.5 V 1.8: 1.8 to 5.5 V
a P
Die Revision
t r
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 1040, Rev. K
REVISION HISTORY
Date 12/09/03 01/21/04 03/13/04 Revision Comments E F G Changed Max Clock Frequency from 6.0V to 5.5V in all instances Changed Endurance Maximum to 100,000 cycles. Eliminated data sheet designation Changed VCC power supply from 1.8V to 6.0V to 1.8V to 5.5V Updated ICC2 Power supply max in DC Operating Characteristics Added package mechanical drawings Eliminated Reel quantity in Ordering Information Update Update Update Update Update D.C. Operating Characteristics Read & Write Cycle Limits Ordering Information Revision History Rev Number
05/16/04
H
06/07/04 7/28/04 08/02/05
I J K
Update Read & Write Cycle Limits Update notes on page 2 Update Pin Configuration Update Ordering Information
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Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
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is D
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Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.caalyst-semiconductor.com
Publication #: Revison: Issue date:
1040 K 08/02/05

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